1. Field of the Invention
The present invention relates to a photoelectric conversion device used in a digital camera, a digital video camera, an endoscope, and the like.
Priority is claimed on Japanese Patent Application No. 2009-208475, filed Sep. 9, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
Conventionally, a solid-state image-pickup device is used as a photoelectric conversion device used in a digital camera, a digital video camera, an endoscope, and the like. Digital cameras, digital video cameras, endoscopes, and the like including the solid-state image-pickup device are increasingly being made smaller and with reduced power consumption. Therefore, there is a need to make the solid-state image-pickup device smaller and with reduced power consumption.
To response to this need, Japanese Unexamined Patent Application, First Publication, No. 2006-287879 discloses a solid-state image-pickup device that internally incorporates an A/D converter configured as a digital circuit.
FIG. 5 is a block diagram illustrating a schematic configuration of a solid-state image-pickup device in accordance with the related art. The solid-state image-pickup device includes a plurality of array blocks (subarrays) arranged in two dimensions. As an example, in the solid-state image-pickup device of FIG. 5, the array blocks (subarrays) B1, B2, . . . , B20 are arranged in four rows and five columns. Each array block (subarray) includes a two-dimensionally arranged pixel block 90 in which a photoelectric conversion element outputs a pixel signal in accordance with an incident light amount, and an A/D converter 9 that converts the pixel signal output from the pixel of the pixel block 90 from analog to digital.
FIG. 6 is a block diagram illustrating an example of a circuit configuration of an A/D converter 9 included in each of the array blocks (subarrays) of FIG. 5. The A/D converter 9 includes a delay circuit 901 and an encoder 902. The delay circuit 901 includes a plurality of delay units, each of which includes various types of gate circuits, and the delay units are connected in a ring shape. An input signal (input voltage) that will be the object of an analog-digital conversion is input to each delay unit in the delay circuit 901 as a drive voltage for the delay units. Also, a reference voltage is supplied to each delay unit in the delay circuit 901.
In the A/D converter 9 of FIG. 6, if, for example, the reference voltage of the delay circuit 901 is GND, and a high-level signal is input as the input pulse signal φPL, then the input pulse signal φPL will have a delay time that corresponds to the voltage difference between the input signal and the reference voltage (GND) as it passes sequentially through the delay units and circulates around the delay circuit 901. If the input pulse signal φPL is set to the low level, then it will stop circulating around the delay circuit 901.
When the input pulse signal φPL is circulating around the delay circuit 901, the number of stages of the delay units that the input pulse signal φPL passes through within a predetermined period of time is determined based on the delay time of the delay units, i.e. the voltage difference between the input signal and the reference voltage (GND). The encoder 902 detects the passed number of stages of delay units (and the number of circulations).
The encoder 902 includes a counter circuit 9021, a latch and encoder circuit 9022, and an adder 9023. The counter circuit 9021 counts the number of circulations of the input pulse signal φPL around the delay circuit 901. The latch and encoder circuit 9022 detects the number of stages of the input pulse signal φPL travelling around the delay circuit 901. The counter circuit 9021 outputs, for example, a bits of upper bit data. The latch and encoder circuit 9022 outputs, for example, b bits of lower bit data. The adder 9023 outputs a+b bits of digital data. The output value of the adder 9023 becomes a digital value after analog-digital conversion in accordance with the voltage of the input signal. In the solid-state image-pickup device of FIG. 5, the pixel signal output from the pixel block 90 is used as the input signal of the A/D converter 9, whereby a digital value in accordance with the incident light amount is output.
FIG. 7 is a block diagram illustrating an example of the photoelectric conversion device that includes the A/D converter 9 of FIG. 6, which is disposed in each column of the pixel array 3. The photoelectric conversion device of FIG. 7 includes pixels P11, . . . , P45, a vertical scanning circuit 4, column circuits 51, . . . , 55, a horizontal scanning circuit 6, a control circuit 7, and A/D converters (ADCs) 91, . . . , 95. A pixel 2 indicates any one of the pixels P11, . . . , P45. A column circuit 5 indicates any one of the column circuits 51, . . . , 55. An ADC 9 indicates any one of the ADCs 91, . . . , 95. In FIG. 7, the pixels P11, . . . , P45 are arranged two-dimensionally in four rows and five columns to configure a pixel array 3. In FIG. 7, signal wires between each delay unit in the delay circuit 901 and the latch and encoder circuit 9022 that are illustrated in FIG. 6 are omitted.
The pixels P11, . . . , P45 are photoelectric conversion elements. If a pixel 2 is selected by the vertical scanning circuit 4, then the pixel 2 outputs a pixel signal which level is based on the incident light amount. The pixels P11, . . . , P45 outputs pixel signals φP1, . . . , φP5 for each column of the pixels in the pixel array 3. The first numerical digit that follows ‘pixel P’ indicates the number of that row in the pixel array 3, and the last numerical digit indicates the number of the column.
The column circuits 51, . . . , 55 are disposed in each column of the pixels in the pixel array 3. The column circuits 51, . . . , 55 process the pixel signal read out from the pixel 2 and output it to the ADCs 91, . . . , 95 of the corresponding column of the pixels. The numerical digit that follows ‘column circuit 5’ of the column circuits 51, . . . , 55 indicates the number of the column in the pixel array 3.
The ADCs 91, . . . , 95 are disposed in each column of the pixels in the pixel array 3. The ADCs 91, . . . , 95 receive the pixel signal that is processed and output from each of the column circuits 51, . . . , 55. Then the ADCs 91, . . . , 95 converts the pixel signal from analog to digital and outputs the converted digital value. Each of the ADCs 91, . . . , 95 has the same circuit configuration as the A/D converter 9 of FIG. 6. The reference voltage (GND) is supplied to the delay circuit 901 in the ADC 9. The numerical digit that follows ‘ADC 9’ of the ADCs 91, . . . , 95 indicates the number of the column in the pixel array 3.
The vertical scanning circuit 4 receives a vertical control signal from the control circuit 7. The vertical scanning circuit 4 selects a row of the pixel 2 that is read out from the pixel array 3 based on the vertical control signal, which is received from the control circuit 7. The vertical scanning circuit 4 outputs row selection signals φSL1, . . . , φSL4 corresponding to the row of the pixel 2 that is read out from the pixel array 3. For example, when the first row of the pixel array 3 is selected, the vertical scanning circuit 4 sets row selection signal φSL1 to the select level (e.g. the high level) and outputs it to the pixel array 3; meanwhile, it sets the unselected row selection signals φSL2, . . . , φSL4 to the non-selected level (e.g. the low level) and outputs them to the pixel array 3.
The horizontal scanning circuit 6 receives a horizontal control signal from the control circuit 7. The horizontal scanning circuit 6 makes the ADCs 91, . . . , 95 output the digital values, which are converted by the ADCs 91, . . . , 95 from analog to digital, in each column based on the horizontal control signal received from the control circuit 7, and sets this output as the output of the photoelectric conversion device. The horizontal scanning circuit 6 outputs column selection signals φH1, . . . , φH5, which correspond to the column of the digital value that is read out from the ADC 9, to the ADC 9. For example, when outputting the digital value of the first column of the pixel array 3, the horizontal scanning circuit 6 sets column selection signal φH1 to the output permission level (e.g. the high level) and outputs it to the ADC 91; meanwhile, it sets the unselected column selection signals φH2, . . . , φH4 to the output not-permitted level (e.g. the low level) and outputs them to the ADCs 92, . . . , 95. The horizontal scanning circuit 6 then sequentially outputs the column selection signals φH2, . . . , φH5 at the output permission level (e.g. the high level), and the other column selection signals φH1, . . . , φH5 corresponding to the non-output columns at the output not-permitted level (e.g. the low level), to the ADC 9. In this way, the horizontal scanning circuit 6 makes the ADC 9 sequentially output the digital values, which the ADC 9 converted from analog to digital.
The control circuit 7 controls the entire photoelectric conversion device. In accordance with an image capture command from an external unit that is not illustrated in the figures, the control circuit 7 outputs a vertical control signal for controlling the vertical scanning circuit 4 and a horizontal control signal for controlling the horizontal scanning circuit 6.
The control circuit 7 also controls the operations (start and stop) of the column circuit 5 and the ADC 9.